#ifndef _DUART_H
#define _DUART_H

/*
 * This file and its contents are supplied under the terms of the
 * Mozilla Public License (MPL) version 2.0.  You may only use this
 * file in accordance with the terms of version 2.0 of the MPL.
 *
 * A full copy of the text of the MPL should have accompanied this
 * source.  A copy of the MPL is also available via the Internet at
 * https://www.mozilla.org/en-CA/MPL/2.0.
 *
 * This Source Code Form is "Incompatible With Secondary Licenses",
 * as defined by the Mozilla Public License, v. 2.0.
 *
 * This is the header file for the Fight Board Dual Asynchronous
 * Receiver Transmitter (DUART) chip, the MC68681.
 *
 * Like the PI/T header, duart_struct is a bit iffy as it relies
 * on unsigned shorts having a word length of 16 bits.  A more
 * modern solution would be to use uint16_ts, but the cc68 compiler
 * originally used predates stdint.h.
 *
 * (C) Copyright Rich Teer 1990, 2023, 2026.
 */

										Here
typedef struct duart_struct {
	unsigned short mra;					/* Mode Register A 1 & 2 (R/W) */
	union {
		unsigned short sra;				/* Status Register A (R) */
		unsigned short csra;			/* Clock-Select Register A (W) */
	} sra_csra;
	union {
		unsigned short ft;				/* Don't use - factory testing only (R) */
		unsigned short cra;				/* Command Register A (W) */
	} ft_cra;
	union {
		unsigned short rba;				/* Receive Buffer A (R) */
		unsigned short tba;				/* Transmit Buffer A (W) */
	} rba_tba;
	union {
		unsigned short ipcr;			/* Input Port Change Register (R) */
		unsigned short acr;				/* Auxiliary Control Register (W) */
	} ipcr_acr;
	union {
		unsigned short isr;				/* Interrupt Status Register (R) */
		unsigned short imr;				/* Interrupt Mask Register (W) */
	} isr_imr;
	union {
		unsigned short cmsb;			/* Current MSB of Counter (counter mode only) (R) */
		unsigned short ctur;			/* Counter/Timer Upper Register (W) */
	} cmsb_ctur;
	union {
		unsigned short clsbr;			/* Current LSB of Counter (counter mode only) (R) */
		unsigned short ctlr;			/* Counter/Timer Lower Register (W) */
	} clsbr_ctlr;
	unsigned short mrb;					/* Mode Register B 1 & 2 (R/W) */
	union {
		unsigned short srb;				/* Status Register B (R) */
		unsigned short csrb;			/* Clock-Select Register B (W) */
	} srb_csrb;
	union {
		unsigned short ft;				/* Don't use, factory testing only (R) */
		unsigned short crb;				/* Command Register B (W) */
	} ft_crb;
	union {
		unsigned short rbb;				/* Receive Buffer B (R) */
		unsigned short tbb;				/* Transmit Buffer B (W) */
	} rbb_tbb;
	union {
		unsigned short ipu;				/* Input Port (Unlatched) (R) */
		unsigned short opcr;			/* Output Port Configuration Register (W) */
	} ipu_opcr;
	union {
		unsigned short scc;				/* Start Counter Command (address triggered) (R) */
		unsigned short bsc;				/* Bit Set Command (address triggered) (W) */
	} scc_bsc;
	union {
		unsigned short scc;				/* Stop Counter Command (address triggered) (R) */
		unsigned short bcc;				/* Bit Clear Command (address triggered) (W) */
	} scc_bcc;
} duart_t;

#endif
